Wireless CMOS Frequency Synthesizer Design

Wireless CMOS Frequency Synthesizer Design

The local oscillator (LO) frequency synthesizer poses some major problems for integration and is the subject of this work. The first, and also the largest, part of this text discusses the design of the Voltage Controlled Oscillator (VCO).

Author: J. Craninckx

Publisher: Springer Science & Business Media

ISBN: 9781475728705

Category: Technology & Engineering

Page: 248

View: 984

The recent boom in the mobile telecommunication market has trapped the interest of almost all electronic and communication companies worldwide. New applications arise every day, more and more countries are covered by digital cellular systems and the competition between the several providers has caused prices to drop rapidly. The creation of this essentially new market would not have been possible without the ap pearance of smalI, low-power, high-performant and certainly low-cost mobile termi nals. The evolution in microelectronics has played a dominant role in this by creating digital signal processing (DSP) chips with more and more computing power and com bining the discrete components of the RF front-end on a few ICs. This work is situated in this last area, i. e. the study of the full integration of the RF transceiver on a single die. Furthermore, in order to be compatible with the digital processing technology, a standard CMOS process without tuning, trimming or post-processing steps must be used. This should flatten the road towards the ultimate goal: the single chip mobile phone. The local oscillator (LO) frequency synthesizer poses some major problems for integration and is the subject of this work. The first, and also the largest, part of this text discusses the design of the Voltage Controlled Oscillator (VCO). The general phase noise theory of LC-oscillators is pre sented, and the concept of effective resistance and capacitance is introduced to char acterize and compare the performance of different LC-tanks.
Categories: Technology & Engineering

Wireless CMOS Frequency Synthesizer Design

Wireless CMOS Frequency Synthesizer Design

The local oscillator (LO) frequency synthesizer poses some major problems for integration and is the subject of this work. The first, and also the largest, part of this text discusses the design of the Voltage Controlled Oscillator (VCO).

Author: J. Craninckx

Publisher:

ISBN: 1475728719

Category:

Page: 276

View: 506

Categories:

Integrated RF CMOS Frequency Synthesizers and Oscillators for Wireless Applications

Integrated RF CMOS Frequency Synthesizers and Oscillators for Wireless Applications

This work investigates the PLL frequency synthesizer design and implementation in CMOS technology with focus on integration of wideband VCOs (Voltage-Controlled Oscillators). Phase noise of a PLL synthesizer is a major design parameter.

Author: Adem Aktas

Publisher:

ISBN: OCLC:58868239

Category: Frequency synthesizers

Page:

View: 444

Abstract: PLL (Phase-Locked Loop) frequency synthesizers are used in wireless transceivers for frequency conversion. Recent directions in PLL frequency synthesizer research and development are to fully integrate PLL synthesizers in CMOS technology, to improve phase noise performance, and to operate wide range of frequency bands and channel bandwidths. Fully integration of synthesizers in CMOS technology is desired for low cost, low power consumption and small size in mobile wireless terminals. Low phase noise is required by digital modulation techniques which have been used in new mobile standards for the efficient use of the frequency spectrum. Operation over a wide range of frequency bands and channel bandwidths are required to support migration and backward compatibility in the wireless standard evolution. This work investigates the PLL frequency synthesizer design and implementation in CMOS technology with focus on integration of wideband VCOs (Voltage-Controlled Oscillators). Phase noise of a PLL synthesizer is a major design parameter. A PLL noise model is developed for noise optimization purposes. Wideband RF VCO design with sub-bands is investigated. Frequency planning, synthesizer architecture and technology considerations are also explored for wideband VCO design. Band switching techniques VCO tuning range presented. Active VCO circuit topologies and resonator design are also presented. The PLL frequency synthesizers are designed and implemented for a multi-band/standard(IEEE 802.11a/b/g) WLAN radio in 0.18um CMOS. Phase noise trade-offs for PLL design are explored in this application. Development and design of a wideband VCO for this application is also presented. An auto calibration circuit is developed for VCO tuning band selection. Another application of the wideband PLL frequency synthesizer is designed and implemented for a fully integrated dual-mode frequency synthesizer for GSM and WCDMA standards in 0.5um CMOS. A hybrid integer-N/fractional-N architecture is developed to meet the multi-standard requirements. Design and implementation of high performance RF VCO depends on the RF models of the devices. RF CMOS characterization and modeling techniques are explored. Microwave wafer measurement and calibration techniques are also investigated for CMOS technology.
Categories: Frequency synthesizers

Multi GHz Frequency Synthesis Division

Multi GHz Frequency Synthesis   Division

In this book, we introduce an alternative solution for conventional flipflop based xiv MULTI–GHZ FREQUENCY SYNTHESIS & DIVISION frequency dividers.

Author: Hamid R. Rategh

Publisher: Springer Science & Business Media

ISBN: 9780306481062

Category: Technology & Engineering

Page: 148

View: 947

In the past 10 years extensive effort has been dedicated to commercial wireless local area network (WLAN) systems. Despite all these efforts, however, none of the existing systems has been successful, mainly due to their low data rates. The increasing demand for WLAN systems that can support data rates in excess of 20 Mb/s enticed the FCC to create an unlicensed national information infrastructure (U–NII) band at 5 GHz. This frequency band provides 300 MHz of spectrum in two segments: a 200 MHz(5.15–5.35 GHz) and a 100 MHz (5.725–5.825 GHz) frequency band. This newly released spectrum, and the fast trend of CMOS scaling, provide an opportunity to design WLAN systems with high data rate and low cost. One of the existing standards at 5 GHz is the European high performance radio LAN (HIPERLAN) standard that supports data rates as high as 20 Mb/s. One of the main building blocks of each wireless system is the f- quency synthesizer. Phase–locked loops (PLLs) are universally used to design radio frequency synthesizers. Reducing the power consumption of the frequency dividers of a PLL has always been a challenge. In this book, we introduce an alternative solution for conventional flipflop based xiv MULTI–GHZ FREQUENCY SYNTHESIS & DIVISION frequency dividers. An injection–locked frequency divider (ILFD) takes advantage of the narrowband nature of the wireless systems and employs resonators to trade off bandwidth for power.
Categories: Technology & Engineering

CMOS PLL Synthesizers Analysis and Design

CMOS PLL Synthesizers  Analysis and Design

This book is useful as a PLL synthesizer manual for both academic researchers and industry design engineers.

Author: Keliu Shu

Publisher: Springer Science & Business Media

ISBN: 9780387236698

Category: Technology & Engineering

Page: 216

View: 679

Thanks to the advance of semiconductor and communication technology, the wireless communication market has been booming in the last two decades. It evolved from simple pagers to emerging third-generation (3G) cellular phones. In the meanwhile, broadband communication market has also gained a rapid growth. As the market always demands hi- performance and low-cost products, circuit designers are seeking hi- integration communication devices in cheap CMOS technology. The phase-locked loop frequency synthesizer is a critical component in communication devices. It works as a local oscillator for frequency translation and channel selection in wireless transceivers and broadband cable tuners. It also plays an important role as the clock synthesizer for data converters in the analog-and-digital signal interface. This book covers the design and analysis of PLL synthesizers. It includes both fundamentals and a review of the state-of-the-art techniques. The transient analysis of the third-order charge-pump PLL reveals its locking behavior accurately. The behavioral-level simulation of PLL further clarifies its stability limit. Design examples are given to clearly illustrate the design procedure of PLL synthesizers. A complete derivation of reference spurs in the charge-pump PLL is also presented in this book. The in-depth investigation of the digital CA modulator for fractional-N synthesizers provides insightful design guidelines for this important block.
Categories: Technology & Engineering

Low Voltage CMOS RF Frequency Synthesizers

Low Voltage CMOS RF Frequency Synthesizers

This book provides the reader with architectures and design techniques to enable CMOS frequency synthesizers to operate at low supply voltage at high frequency with good phase noise and low power consumption.

Author: Howard Cam Luong

Publisher: Cambridge University Press

ISBN: 1139454579

Category: Technology & Engineering

Page: 180

View: 295

A frequency synthesizer is one of the most critical building blocks in any wireless transceiver system. Its design is getting more and more challenging as the demand for low-voltage low-power high-frequency wireless systems continuously grows. As the supply voltage is decreased, many existing design techniques are no longer applicable. This book provides the reader with architectures and design techniques to enable CMOS frequency synthesizers to operate at low supply voltage at high frequency with good phase noise and low power consumption. In addition to updating the reader on many of these techniques in depth, this book will also introduce useful guidelines and step-by-step procedure on behaviour simulations of frequency synthesizers. Finally, three successfully demonstrated CMOS synthesizer prototypes with detailed design consideration and description will be elaborated to illustrate potential applications of the architectures and design techniques described. For engineers, managers and researchers working in radio-frequency integrated-circuit design for wireless applications.
Categories: Technology & Engineering

Integrated Frequency Synthesizers for Wireless Systems

Integrated Frequency Synthesizers for Wireless Systems

This book contains everything you need to know for the efficient design of frequency synthesizers for today's communications applications. If you need to optimize performance and minimize design time, you will find this book invaluable.

Author: Andrea Leonardo Lacaita

Publisher: Cambridge University Press

ISBN: 9781139466097

Category: Technology & Engineering

Page:

View: 442

The increasingly demanding performance requirements of communications systems, as well as problems posed by the continued scaling of silicon technology, present numerous challenges for the design of frequency synthesizers in modern transceivers. This book contains everything you need to know for the efficient design of frequency synthesizers for today's communications applications. If you need to optimize performance and minimize design time, you will find this book invaluable. Using an intuitive yet rigorous approach, the authors describe simple analytical methods for the design of phase locked loop (PLL) frequency synthesizers using scaled silicon CMOS and bipolar technologies. The entire design process, from system-level specification to layout, is covered comprehensively. Practical design examples are included, and implementation issues are addressed. A key problem-solving resource for practitioners in IC design, the book will also be of interest to researchers and graduate students in electrical engineering.
Categories: Technology & Engineering

All Digital Frequency Synthesizer in Deep Submicron CMOS

All Digital Frequency Synthesizer in Deep Submicron CMOS

This book is a must-read for students and engineers who want to learn a new paradigm for RF frequency synthesis and wireless transmitter design using digitally intensive design techniques.

Author: Robert Bogdan Staszewski

Publisher: John Wiley & Sons

ISBN: 9780470041949

Category: Technology & Engineering

Page: 220

View: 346

A new and innovative paradigm for RF frequency synthesis and wireless transmitter design Learn the techniques for designing and implementing an all-digital RF frequency synthesizer. In contrast to traditional RF techniques, this innovative book sets forth digitally intensive design techniques that lead the way to the development of low-cost, low-power, and highly integrated circuits for RF functions in deep submicron CMOS processes. Furthermore, the authors demonstrate how the architecture enables readers to integrate an RF front-end with the digital back-end onto a single silicon die using standard ASIC design flow. Taking a bottom-up approach that progressively builds skills and knowledge, the book begins with an introduction to basic concepts of frequency synthesis and then guides the reader through an all-digital RF frequency synthesizer design: Chapter 2 presents a digitally controlled oscillator (DCO), which is the foundation of a novel architecture, and introduces a time-domain model used for analysis and VHDL simulation Chapter 3 adds a hierarchical layer of arithmetic abstraction to the DCO that makes it easier to operate algorithmically Chapter 4 builds a phase correction mechanism around the DCO such that the system's frequency drift or wander performance matches that of the stable external frequency reference Chapter 5 presents an application of the all-digital RF synthesizer Chapter 6 describes the behavioral modeling and simulation methodology used in design The final chapter presents the implementation of a full transmitter and experimental results. The novel ideas presented here have been implemented and proven in two high-volume, commercial single-chip radios developed at Texas Instruments: Bluetooth and GSM. While the focus of the book is on RF frequency synthesizer design, the techniques can be applied to the design of other digitally assisted analog circuits as well. This book is a must-read for students and engineers who want to learn a new paradigm for RF frequency synthesis and wireless transmitter design using digitally intensive design techniques.
Categories: Technology & Engineering

Design of CMOS Integrated Frequency Synthesizers for Ultra wideband Wireless Communications Systems

Design of CMOS Integrated Frequency Synthesizers for Ultra wideband Wireless Communications Systems

Ultra℗Ơwide band (UWB) system is a breakthrough in wireless communication, as it provides data rate one order higher than existing ones.

Author: Haitao Tong

Publisher:

ISBN: OCLC:609886224

Category:

Page:

View: 498

Ultra℗Ơwide band (UWB) system is a breakthrough in wireless communication, as it provides data rate one order higher than existing ones. This dissertation focuses on the design of CMOS integrated frequency synthesizer and its building blocks used in UWB system. A mixer℗Ơbased frequency synthesizer architecture is proposed to satisfy the agile frequency hopping requirement, which is no more than 9.5 ns, three orders faster than conventional phase℗Ơlocked loop (PLL)℗Ơbased synthesizers. Harmonic cancela℗Ơtion technique is extended and applied to suppress the undesired harmonic mixing components. Simulation shows that sidebands at 2.4 GHz and 5 GHz are below 36 dBc from carrier. The frequency synthesizer contains a novel quadrature VCO based on the capacitive source degeneration structure. The QVCO tackles the jeopardous ambiguity of the oscillation frequency in conventional QVCOs. Measurement shows that the 5℗ƠGHz CSD℗ƠQVCO in 0.18 ℗æm CMOS technology draws 5.2 mA current from a 1.2 V power supply. Its phase noise is ℗Ơ120 dBc at 3 MHz oƠ̐0set. Compared with existing phase shift LC QVCOs, the proposed CSD℗ƠQVCO presents better phase noise and power eƠ̐3ciency. Finally, a novel injection locking frequency divider (ILFD) is presented. Im℗Ơplemented with three stages in 0.18 ℗æm CMOS technology, the ILFD draws 3℗ƠmA current from a 1.8℗ƠV power supply. It achieves multiple large division ratios as 6, 12, and 18 with all locking ranges greater than 1.7 GHz and injection frequency up to 11 GHz. Compared with other published ILFDs, the proposed ILFD achieves the largest division ratio with satisfactory locking range.
Categories:

Fully integrated DLL PLL based CMOS Frequency Synthesizers for Wireless Systems

Fully integrated DLL PLL based CMOS Frequency Synthesizers for Wireless Systems

A frequency synthesizer plays a critical role in defining the performance of wireless systems in terms of measures such as operating frequency range, settling time, phase noise and spur performance, and area/power consumption.

Author: Jaehyouk Choi

Publisher:

ISBN: OCLC:794446859

Category: Frequency synthesizers

Page:

View: 600

A frequency synthesizer plays a critical role in defining the performance of wireless systems in terms of measures such as operating frequency range, settling time, phase noise and spur performance, and area/power consumption. As the trend in mobile system design has changed from single-standard systems to multi-standard/multi-application systems, the role of frequency synthesizers has become even more important. : As the most popular architecture, a phase-locked loop (PLL)-based frequency synthesizer has been researched over the last several decades; however, many unsolved problems related to the PLL-based synthesizer are still waiting for answers. This dissertation addresses key challenges related to fully integrated PLL-based frequency synthesizers, including the problem of large area consumption of passive components, the inherent reference-spur problem, and the problem of trade-offs between integer-N PLLs and fractional-N PLLs.
Categories: Frequency synthesizers

CMOS PLLs and VCOs for 4G Wireless

CMOS PLLs and VCOs for 4G Wireless

As such, this book discusses design, modeling and optimization techniques for low power fully integrated broadband PLLs and VCOs in deep submicron CMOS.

Author: Adem Aktas

Publisher: Springer Science & Business Media

ISBN: 9781402080609

Category: Technology & Engineering

Page: 175

View: 457

CMOS PLLs and VCOs for 4G Wireless is the first book devoted to the subject of CMOS PLL and VCO design for future broadband 4th generation wireless devices. These devices will be handheld-centric, requiring very low power consumption and small footprint. They will be able to work across multiple bands and multiple standards covering WWAN (GSM,WCDMA) ,WLAN(802.11 a/b/g) and WPAN(Bluetooth) with different modulations, channel bandwidths , phase noise requirements ,etc. As such, this book discusses design, modeling and optimization techniques for low power fully integrated broadband PLLs and VCOs in deep submicron CMOS. First, the PLL and VCO performances are studied in the context of the chosen multi-band multi-standard, radio architecture and the adopted frequency plan. Next a thorough study of the design requirements for broadband PLL/VCO design is conducted together with modeling techniques for noise sources in a PLL and VCO focusing on optimization of integrated phase noise for multi-carrier OFDM 64-QAM type applications. Design examples for multi-standard 802.111a/b/g as well as for GSM/WCDMA are fully described and experimental results from 0.18 micron CMOS test chips have demonstrated the validity of the proposed design and optimization techniques. Equally important the work describes techniques for robust high volume production of RF radios in general and for integrated PLL/VCO design in particular including issues such as supply sensitivity, ground bounce and calibration mechanisms. CMOS PLLS and VCOs for 4G Wireless will be of interest to graduate students in electrical and computer engineering, design managers and RFIC designers in wireless semiconductor companies.
Categories: Technology & Engineering

Multi Ghz Frequency Synthesis and Division

Multi Ghz Frequency Synthesis and Division

In this book, we introduce an alternative solution for conventional flipflop based xiv MULTI–GHZ FREQUENCY SYNTHESIS & DIVISION frequency dividers.

Author: Hamid R. Rategh

Publisher:

ISBN: 1475774990

Category:

Page: 172

View: 575

Categories:

Clock Generators for SOC Processors

Clock Generators for SOC Processors

This book examines the issue of design of fully-integrated frequency synthesizers suitable for system-on-a-chip (SOC) processors.

Author: Amr Fahim

Publisher: Springer Science & Business Media

ISBN: 1402080794

Category: Technology & Engineering

Page: 245

View: 850

This book examines the issue of design of fully-integrated frequency synthesizers suitable for system-on-a-chip (SOC) processors. This book takes a more global design perspective in jointly examining the design space at the circuit level as well as at the architectural level. The coverage of the book is comprehensive and includes summary chapters on circuit theory as well as feedback control theory relevant to the operation of phase locked loops (PLLs). On the circuit level, the discussion includes low-voltage analog design in deep submicron digital CMOS processes, effects of supply noise, substrate noise, as well device noise. On the architectural level, the discussion includes PLL analysis using continuous-time as well as discrete-time models, linear and nonlinear effects of PLL performance, and detailed analysis of locking behavior. The material then develops into detailed circuit and architectural analysis of specific clock generation blocks. This includes circuits and architectures of PLLs with high power supply noise immunity and digital PLL architectures where the loop filter is digitized. Methods of generating low-spurious sampling clocks for discrete-time analog blocks are then examined. This includes sigma-delta fractional-N PLLs, Direct Digital Synthesis (DDS) techniques and non-conventional uses of PLLs. Design for test (DFT) issues as they arise in PLLs are then discussed. This includes methods of accurately measuring jitter and built-in-self-test (BIST) techniques for PLLs. Finally, clocking issues commonly associated to system-on-a-chip (SOC) designs, such as multiple clock domain interfacing and partitioning, and accurate clock phase generation techniques using delay-locked loops (DLLs) are also addressed. The book provides numerous real world applications, as well as practical rules-of-thumb for modern designers to use at the system, architectural, as well as the circuit level. This book is well suited for practitioners as well as graduate level students who wish to learn more about time-domain analysis and design of frequency synthesis techniques.
Categories: Technology & Engineering

Design Methodology for RF CMOS Phase Locked Loops

Design Methodology for RF CMOS Phase Locked Loops

The book includes design alternatives for phase detectors that feature methods to minimize jitter caused by the dead zone effect.

Author: Carlos Quemada

Publisher: Artech House

ISBN: 9781596933842

Category: Electrical engineering

Page: 242

View: 898

After a review of PLL essentials, this uniquely comprehensive workbench guide takes you step-by-step through operation principles, design procedures, phase noise analysis, layout considerations, and CMOS realizations for each PLL building block. You get full details on LC tank oscillators including modeling and optimization techniques, followed by design options for CMOS frequency dividers covering flip-flop implementation, the divider by 2 component, and other key factors. The book includes design alternatives for phase detectors that feature methods to minimize jitter caused by the dead zone effect. You also find a sample design of a fully integrated PLL for WLAN applications that demonstrates every step and detail right down to the circuit schematics and layout diagrams. Supported by over 150 diagrams and photos, this one-stop toolkit helps you produce superior PLL designs faster, and deliver more effective solutions for low-cost integrated circuits in all RF applications.
Categories: Electrical engineering

CMOS Single Chip Fast Frequency Hopping Synthesizers for Wireless Multi Gigahertz Applications

CMOS Single Chip Fast Frequency Hopping Synthesizers for Wireless Multi Gigahertz Applications

In this book, the authors outline detailed design methodology for fast frequency hopping synthesizers for RF and wireless communications applications.

Author: Taoufik Bourdi

Publisher: Springer Science & Business Media

ISBN: 9781402059285

Category: Technology & Engineering

Page: 208

View: 250

In this book, the authors outline detailed design methodology for fast frequency hopping synthesizers for RF and wireless communications applications. There is great emphasis on fractional-N delta-sigma based phase locked loops from specifications, system analysis and architecture planning to circuit design and silicon implementation. The developed techniques in the book can help in designing very low noise, high speed fractional-N frequency synthesizers.
Categories: Technology & Engineering

A 1 5 V 900 Mhz Monolithic CMOS Fast switching Frequency Synthesizer for Wireless Applications

A 1 5 V 900 Mhz Monolithic CMOS Fast switching Frequency Synthesizer for Wireless Applications

In modern transceiver designs, a frequency synthesizer with good phase-noise performance is very important because it affects the efficiency of valuable air channel usage and sensitivity of small signals under the presence of large ...

Author:

Publisher:

ISBN: OCLC:697521997

Category:

Page:

View: 663

In modern transceiver designs, a frequency synthesizer with good phase-noise performance is very important because it affects the efficiency of valuable air channel usage and sensitivity of small signals under the presence of large interference. Fast frequency switching is also required in many TDMA systems and frequency-hopping spread-spectrum systems. Other than these, low supply voltage, low power consumption and monolithic design are three important features of any modern analog circuits. However, the above requirements are difficult to be achieved in traditional frequency synthesizer designs. To solve these problems, a new design of phase-locked loop frequency synthesizer is proposed. Instead of voltage or current domain, some signals in the phase-locked loop are manipulated in capacitance domain. A binary-weighted switchable-capacitor array is used to replace the digital-to-analog converter while two varactors connected in parallel replace the voltage adder. This design provides many advantages, including simplified analog circuitry, low supply voltage, low power consumption, small chip area, fast frequency switching and high immunity of substrate noise. A prototype of a 1.5-V 900-Mhz monolithic CMOS fast-switching frequency synthesizer based on GSM specifications is designed and fabricated to demonstrate the idea. It consumes 30mW. The total chip area is 0.9 x 1.1 mm2. The settling time is within 150us and phase noise is -118dBc/Hz at 600kHz offset. The ability of direct-digital modulation is also provided with the sigma-delta fractional-N architecture.
Categories:

60 GHz CMOS Phase Locked Loops

60 GHz CMOS Phase Locked Loops

Abstract This chapter lays the foundation for the work presented in latter chapters.

Author: Hammad M. Cheema

Publisher: Springer Science & Business Media

ISBN: 9789048192809

Category: Technology & Engineering

Page: 197

View: 667

Abstract This chapter lays the foundation for the work presented in latter chapters. The potential of 60 GHz frequency bands for high data rate wireless transfer is discussed and promising applications are enlisted. Furthermore, the challenges related to 60 GHz IC design are presented and the chapter concludes with an outline of the book. Keywords Wireless communication 60 GHz Millimeter wave integrated circuit design Phase-locked loop CMOS Communication technology has revolutionized our way of living over the last century. Since Marconi’s transatlantic wireless experiment in 1901, there has been tremendous growth in wireless communication evolving from spark-gap telegraphy to today’s mobile phones equipped with Internet access and multimedia capabilities. The omnipresence of wireless communication can be observed in widespread use of cellular telephony, short-range communication through wireless local area networks and personal area networks, wireless sensors and many others. The frequency spectrum from 1 to 6 GHz accommodates the vast majority of current wireless standards and applications. Coupled with the availability of low cost radio frequency (RF) components and mature integrated circuit (IC) techn- ogies, rapid expansion and implementation of these systems is witnessed. The downside of this expansion is the resulting scarcity of available bandwidth and allowable transmit powers. In addition, stringent limitations on spectrum and energy emissions have been enforced by regulatory bodies to avoid interference between different wireless systems.
Categories: Technology & Engineering